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Silicon Labs /Series0 /EZR32HG /EZR32HG320F32R69 /USB /DCFG

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Interpret as DCFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0DEVSPD 0 (NZSTSOUTHSHK)NZSTSOUTHSHK 0 (ENA32KHZSUSP)ENA32KHZSUSP 0DEVADDR0 (80PCNT)PERFRINT 0 (ERRATICINTMSK)ERRATICINTMSK 0RESVALID

PERFRINT=80PCNT

Description

Device Configuration Register

Fields

DEVSPD

Device Speed

2 (LS): Low speed (PHY clock is 6 MHz). If you select 6 MHz LS mode, you must do a soft reset.

3 (FS): Full speed (PHY clock is 48 MHz).
NZSTSOUTHSHK

Non-Zero-Length Status OUT Handshake
ENA32KHZSUSP

Enable 32 KHz Suspend mode
DEVADDR

Device Address
PERFRINT

Periodic Frame Interval

0 (80PCNT): 80% of the frame interval.

1 (85PCNT): 85% of the frame interval.

2 (90PCNT): 90% of the frame interval.

3 (95PCNT): 95% of the frame interval.
ERRATICINTMSK
RESVALID

Resume Validation Period

Links

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Register License

  • SPDX-License-Identifier: Zlib
  • The licensor of this software is Silicon Laboratories Inc.
  • This software is provided ‘as-is’, without any express or implied
  • warranty. In no event will the authors be held liable for any damages
  • arising from the use of this software.
  • Permission is granted to anyone to use this software for any purpose,
  • including commercial applications, and to alter it and redistribute it
  • freely, subject to the following restrictions:
    1. The origin of this software must not be misrepresented; you must not
  • claim that you wrote the original software. If you use this software
  • in a product, an acknowledgment in the product documentation would be
  • appreciated but is not required.
    1. Altered source versions must be plainly marked as such, and must not be
  • misrepresented as being the original software.
    1. This notice may not be removed or altered from any source distribution.
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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data